? 2001 fairchild semiconductor corporation ds011352 www.fairchildsemi.com february 1992 revised june 2001 74lvq157 low voltage quad 2-input multiplexer 74lvq157 low voltage quad 2-input multiplexer general description the lvq157 is a high-speed quad 2-input multiplexer. four bits of data from two sources can be selected using the common select and enable inputs. the four outputs present the selected data in the true (non inverted) form. the lvq157 can also be used as a function generator. features ideal for low power/low noise 3.3v applications guaranteed simultaneous switching noise level and dynamic threshold performance guaranteed pin-to-pin skew ac performance guaranteed incident wave switching into 75 ? . ordering code: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. logic symbols ieee/iec connection diagram pin descriptions order number package number package description 74lvq157sc m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74lvq157sj m16d 16-lead small outline package (sop), eiaj type ii, 5.3mm wide pin names description i 0a ? i 0d source 0 data inputs i 1a ? i 1d source 1 data inputs e enable input s select input z a ? z d outputs
www.fairchildsemi.com 2 74lvq157 truth table h = high voltage level l = low voltage level x = immaterial functional description the lvq157 is a quad 2-input multiplexer. it selects four bits of data from two sources under the control of a com- mon select input (s). the enable input (e ) is active-low. when e is high, all of the outputs (z) are forced low regardless of all other inputs. the lvq157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels sup- plied to the select input. the logic equations for the outputs are shown below: z a = e (i 1a s + i 0a s ) z b = e (i 1b s + i 0b s ) z c = e (i 1c s + i 0c s ) z d = e (i 1d s + i 0d s ) a common use of the lvq157 is the moving of data from two groups of registers to four common output busses. the particular register from which the data comes is determined by the state of the select input. a less obvious use is as a function generator. the lvq157 can generate any four of the sixteen different functions of two variables with one variable common. this is useful for implementing gating functions. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. inputs outputs e si 0 i 1 z hx x x l lh x l l lh x h h ll l x l ll h x h
3 www.fairchildsemi.com 74lvq157 absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: unused inputs must be held high or low. they may not float. dc electrical characteristics note 3: all outputs loaded; thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: incident wave switching on transmission lines with impedances as low as 75 ? for commercial temperature range is guaranteed for. note 6: worst case package. note 7: max number of outputs defined as (n). data inputs are driven 0v to 3.3v; one output at gnd. note 8: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to 3.3v. input-under-test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f = 1 mhz. supply voltage (v cc ) ? 0.5v to + 7.0v dc input diode current (i ik ) v i = ? 0.5v ? 20 ma v i = v cc + 0.5v + 20 ma dc input voltage (v i ) ? 0.5v to v cc + 0.5v dc output diode current (i ok ) v o = ? 0.5v ? 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) ? 0.5v to v cc + 0.5v dc output source or sink current (i o ) 50 ma dc v cc or ground current (i cc or i gnd ) 200 ma storage temperature (t stg ) ? 65 c to + 150 c dc latch-up source or sink current 100 ma supply voltage (v cc ) 2.0v to 3.6v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( ? v/ ? t) v in from 0.8v to 2.0v v cc @ 3.0v 125 mv/ns symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.0 2.0 v v out = 0.1v input voltage or v cc ? 0.1v v il maximum low level 3.0 1.5 0.8 0.8 v v out = 0.1v input voltage or v cc ? 0.1v v oh minimum high level 3.0 2.99 2.9 2.9 v i out = ? 50 a output voltage 3.0 2.58 2.48 v v in = v il or v ih (note 3) i oh = ? 12 ma v ol maximum low level 3.0 0.002 0.1 0.1 v i out = 50 a output voltage 3.0 0.36 0.44 v v in = v il or v ih (note 3) i ol = 12 ma i in maximum input 3.6 0.1 1.0 a v i = v cc , leakage current gnd i old minimum dynamic 3.6 36 ma v old = 0.8v max (note 5) i ohd output current (note 4) 3.6 ? 25 ma v ohd = 2.0v min (note 5) i cc maximum quiescent 3.6 4.0 40.0 a v in = v cc supply current or gnd v olp quiet output 3.3 0.7 0.8 v (note 6)(note 7) maximum dynamic v ol v olv quiet output 3.3 ? 0.4 ? 0.8 v (note 6)(note 7) minimum dynamic v ol v ihd maximum high level 3.3 1.7 2.0 v (note 6)(note 8) dynamic input voltage v ild maximum low level 3.3 1.6 0.8 v (note 6)(note 8) dynamic input voltage
www.fairchildsemi.com 4 74lvq157 ac electrical characteristics note 9: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. capacitance note 10: c pd is measured at 10 mhz. symbol parameter t a = + 25 ct a = ? 40 c to + 85 c units v cc c l = 50 pf c l = 50 pf (v) min typ max min max t plh propagation delay 2.7 1.5 84 16.2 1.5 19.0 ns s to z n 3.3 0.3 1.5 7.0 11.5 1.5 13.0 t phl propagation delay 2.7 1.5 7.8 15.5 1.5 17.0 ns s to z n 3.3 0.3 1.5 6.5 11.0 1.5 12.0 t plh propagation delay 2.7 1.5 8.4 16.2 1.5 19.0 ns e to z n 3.3 0.3 1.5 7.0 11.5 1.5 13.0 t phl propagation delay 2.7 1.5 7.8 15.5 1.5 17.0 ns e to z n 3.3 0.3 1.5 6.5 11.0 1.5 12.0 t plh propagation delay 2.7 1.5 6.0 12.0 1.0 13.0 ns i n to z n 3.3 0.3 1.5 5.0 8.5 1.0 9.0 t phl propagation delay 2.7 1.5 6.0 11.3 1.0 13.0 ns i n to z n 3.3 0.3 1.5 5.0 8.0 1.0 9.0 t oshl, output to output skew (note 9) 2.7 1.0 1.5 1.5 ns t oslh data to output 3.3 0.3 1.0 1.5 1.5 symbol parameter typ units conditions c in input capacitance 4.5 pf v c = open c pd (note 10) power dissipation capacitance 34.0 pf v cc = 3.3v
5 www.fairchildsemi.com 74lvq157 physical dimensions inches (millimeters) unless otherwise noted 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m16a
www.fairchildsemi.com 6 74lvq157 low voltage quad 2-input multiplexer physical dimensions inches (millimeters) unless otherwise noted (continued) 16-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m16d fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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